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* this document contains cert ain information on a new product. specifications and information herein are subject to change without notice. document number: mc34gd3000 rev. 3.0, 5/2016 nxp semiconductors data sheet: advance information ? 2016 nxp b.v. three phase field effect transistor pre-driver the 34gd3000 is a field effect transisto r (fet) pre-drivers designed for three phase motor control and similar applications. the integrated circuit (ic) uses smartmos technology. the ic contains three high-side fet pr e-drivers and three low-side fet pre- drivers. three external bo otstrap capacitors provide gate charge to the high- side fets. the ic interfaces to a mcu via six direct input control signals, an spi port for device setup and asynchronous reset, enable and interrupt signals. both 5.0 v and 3.3 v logic level inputs are accept ed and 5.0 v logic level outputs are provided. features ? extended supply voltage operating range: 6.0 v to 60 v ? wide dead time range (50 ns to 12 s) programmable via the spi port ? gate drive capability of 1.0 a to 2.5 a ? charge pump ensures sufficient extern al fet drive at low supply voltages ? device protection against reve rse charge-injection from c gd and c gs of external fets ? integrated overcurr ent, desaturation, and phase fault-detection ? immunity against positive or negative transient voltage spikes on the gate driver ? current shoot-through protection built into dead time control ? supports direct 3.3 v and 5.0 v logic interface to mcus ? integrated current sensing amplifier ? device configuration and diagnostics through the spi figure 1. 34gd3000 simpli fied application diagram three phase pre-driver ep suffix (pb-free) 98asa00654d 56-pin qfn applications ? 12 v - 48 v 3-phase brushless dc (bldc) motors and permanent magnet synchronous motors (pmsm) ? pool pumps, hospital beds, electric scooters ? industrial robotics, pumps and fans ? portable power tools, commercial fans/blowers ? small kitchen appliances 34gd3000 industrial vpump pump vsup vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int pa_hs_g pb_hs_g pc_hs_g pa_hs_s pb_hs_s pc_hs_s pa_ls_g pb_ls_g pc_ls_g px_ls_s amp_p amp_n amp_out gnd 34gd3000 v sys mcu or dsp 3 3 3 r sen en1 vss en2
2 nxp semiconductors 34gd3000 1 orderable parts table 1. orderable part variations part number (1) temperature (t a ) package MC34GD3000EP -20 c to 105 c 56 pin qfn notes 1. to order parts in tape & reel, add the r2 suffix to the part number.
nxp semiconductors 3 34gd3000 2 internal block diagram figure 2. 34gd3000 simplified internal block diagram vpump pump vsup vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int amp_p amp_n amp_out px_ls_s main charge pump pgnd en1 en2 oc_out gnd(2) px_boot px_hs_g px_hs_s px_ls_g oc_th vls_cap trickle charge pump hold -off circuit oscillator control logic 5.0 v reg. v dd v ls reg. uv detect t-lim + - + - + - 1.4 v + - v sup v sup + - overcurrent. comp. i-sense amp. high- side driver low- side driver 3 3 3 3x desat. comp phase comp. vss
4 nxp semiconductors 34gd3000 3 pin connections figure 3. 34gd3000 pin connections a functional description of each pin can be found in the functional pin description section beginning on page 20 . table 2. 34gd3000 pin definitions pin pin name pin function formal name definition 1 pa_boot analog input phase a bootstrap bootstrap capacitor for phase a 2, 3, 5, 7, 13, 17, 41, 42 nc no connect no connection 4 vls analog output vls regulator vls regulator output; power supply for the gate drives 6 vpwr power input voltage power power supply input for gate drives 8 phasea digital output phase a totem pole output of phase a comparator; this output is low when the voltage on pa_hs_s (source of high-side fet) is less than 50% of v sup 9 pgnd ground power ground power ground for charge pump 10 en1 digital input enable 1 logic signal input must be high (anded with en2) to enable any gate drive output. 11 en2 digital input enable 2 logic signal input must be high (anded with en1) to enable any gate drive output pa_boot nc nc vls nc vpwr nc phasea pgnd en1 en2 rst_b nc pump vpump vsup nc phaseb phasec pa_hs_b pa_ls vdd pb_hs_b pb_ls int cs_b si pa_ls_g pa_ls_s pb_boot pb_hs_g pb_ls_s pb_ls_g pb_hs_s pc_boot pc_hs_s pc_hs_g pc_ls_s nc nc vls_cap gnd gnd vss oc_th oc_out amp_p amp_n amp_out pc_hs_b pc_ls so sclk transparent top view pa_hs_g pa_hs_s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ep pc_ls_g
nxp semiconductors 5 34gd3000 12 rst_b digital input reset reset input 14 pump power drive out pump charge pump output 15 vpump power input voltage pump charge pump supply 16 vsup analog input supply voltage supply voltage to the load. this pi n is to be connected to the common drains of the external high-side fets 18 phaseb digital output phase b totem pole output of phase b comparator. this output is low when the voltage on pb_hs_s (source of high-side fet) is less than 50% of v sup 19 phasec digital output phase c totem pole output of phase c comparator. this output is low when the voltage on pc_hs_s (source of high-side fet) is less than 50% of v sup 20 pa_hs_b digital input phase a high-side active low input logic signal enabl es the high-side driver for phase a 21 pa_ls digital input phase a low-side active high input logic signal enabl es the low-side driver for phase a 22 vdd analog output vdd regulator vdd regulator output capacitor connection 23 pb_hs_b digital input phase b high-side active low input logic signal enabl es the high-side driver for phase b 24 pb_ls digital input phase b low-side active high input logic signal enabl es the low-side driver for phase b 25 int digital output interrupt interrupt pin output 26 cs_b digital input chip select chip select input. it frames spi commands and enables spi port 27 si digital input serial in input data for spi port. clocked on the falling edge of sclk, msb first 28 sclk digital input serial clock clock for spi port and typically is 3.0 mhz 29 so digital output serial out output data for spi port. tri-state until cs becomes low 30 pc_ls digital input phase c low-side active high input logic signal enabl es the low-side driver for phase c 31 pc_hs_b digital input phase c high-side active low input logic signal enabl es the high-side driver for phase c 32 amp_out analog output amplifier output output of the current-sensing amplifier 33 amp_n analog input amplifier invert inverting input of the current-sensing amplifier 34 amp_p analog input amplifier non-invert non-inverting input of the current-sensing amplifier 35 oc_out digital output overcurrent out totem pole digital output of the overcurrent comparator 36 oc_th analog input overcurrent threshold threshold of the overcurrent detector 37 vss ground voltage source supply ground reference for logic interface and power supplies 38, 39 gnd ground ground substrate and esd reference, connect to vss 40 vls_cap analog output vls regulator output capacitor vls regulator connection for additional output capacitor, providing low impedance supply source for low-side gate drive 43 pc_ls_s power input phase c low-side source source connection for phase c low-side fet 44 pc_ls_g power output phase c low-side gate drive gate drive output for phase c low-side 45 pc_hs_s power input phase c high-side source source connection for phase c high-side fet 46 pc_hs_g power output phase c high-side gate drive gate drive for output phase c high-side fet 47 pc_boot analog input phase c bootstrap bootstrap capacitor for phase c table 2. 34gd3000 pin definitions pin pin name pin function formal name definition
6 nxp semiconductors 34gd3000 48 pb_ls_s power input phase b low-side source source connection for phase b low-side fet 49 pb_ls_g power output phase b low-side gate drive gate drive for output phase b low-side 50 pb_hs_s power input phase b high-side source source connection for phase b high-side fet 51 pb_hs_g power output phase b high-side gate drive gate drive for output phase b high-side 52 pb_boot analog input phase b bootstrap bootstrap capacitor for phase b 53 pa_ls_s power input phase a low-side source source connection for phase a low-side fet 54 pa_ls_g power output phase a low-side gate drive gate drive for output phase a low-side 55 pa_hs_s power input phase a high-side source source connection for phase a high-side fet 56 pa_hs_g power output phase a high-side gate drive gate drive for output phase a high-side ep ground exposed pad device performs as specified with the exposed pad un-terminated (floating) however, it is recommended the exposed pad be terminated to pin 29 (vss) and system ground table 2. 34gd3000 pin definitions pin pin name pin function formal name definition
nxp semiconductors 7 34gd3000 4 electrical characteristics 4.1 maximum ratings table 3. maximum ratings all voltages are with respect to v ss unless otherwise noted. exceeding these ratings ma y cause a malfunction or permanent damage to the device. symbol ratings value unit notes electrical ratings v sup vsup supply voltage ? normal operation (steady-state) ? transient survival 60 -1.5 to 80 v (2) v pwr vpwr supply voltage ? normal operation (steady-state) ? transient survival 58 -1.5 to 80 v (2) v pump charge pump (pump, vpump) -0.3 to 40 v v ls vls regulator outputs (vls , vls_cap) -0.3 to 18 v v dd logic supply voltage -0.3 to 7.0 v v out logic output (int, so, phasea, phaseb, phasec, oc_out) -0.3 to 7.0 v (3) v in logic input pin voltage (en1, en2, px_hs, px_ls, si, sclk, cs, rst) 10 ma -0.3 to 7.0 v v in_a amplifier input voltage ? (both inputs-gnd), (amp_p - g nd) or (amp_n - gnd) 6.0 ma source or sink -7.0 to 7.0 v v oc overcurrent comparator threshold 10 ma -0.3 to 7.0 v v boot v hs_g v ls_g driver output voltage ? high-side bootstrap (pa_boot, pb_boot, pc_boot) ? high-side (pa_hs_g, pb_hs_g, pc_hs_g) ? low-side (pa_ls_g, pb_ls_g, pc_ls_g) 75 75 16 v (4) v hs_g v hs_s v ls_g v ls_s driver voltage transient survival ? high-side (pa_hs_g, pb_hs_g, pc_hs_g, pa_hs_s, pb_hs_s, pc_hs_s) ? low-side (pa_ls_g, pb_ls_g, pc_ls_g, pa_ls_s, pb_ls_s, pc_ls_s) -7.0 to 75.0 -7.0 to 75.0 -7.0 to 18.0 -7.0 to 7.0 v (5) v esd esd voltage ? human body model - hbm (all pins except for the pins listed below) pins: pa_boot, pa_hs_s, pa_hs_g, pb_boot, pb_hs_s, pb_hs_g, pc_boot, pc_hs_s, pc_hs_g, vpwr ? charge device model - cdm ? corner pins ? all other pins 2000 1000 750 300 v (6) notes 2. the device can withstand a voltage transient as defined by iso7637 with peak voltage of 80 v. 3. short-circuit proof, the device is not be damaged or induce unexpected behavior due to shorts to external sources within this range. 4. this voltage should not be applied without also taking voltage at hs_s and voltage at px_ls_s into account. 5. actual operational limitations may di ffer from survivabili ty limits. the v ls - v ls_s differential and the v boot - v hs_s differential must be greater than 3.0 v to insure the output gate drive maintains a commanded off condition on the output. 6. esd testing is performed in accor dance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ) and the charge device model (cdm), robotic (c zap = 4.0 pf).
8 nxp semiconductors 34gd3000 thermal ratings t stg storage temperature -55 to +150 c t j operating junction temperature -40 to +150 c (7) r jc thermal resistance ? junction-to-case 1.5 c/w (8) t solder soldering temperature note 10 c (9) notes 7. in order to meet or exceed the expected reliability performanc e level over 10 years of continuous operation, the user must ta ke measures to guarantee the device?s average junction temperature does not exceed 125 oc. the device?s maximum junction te mperature remains as specified in the data sheet. 8. case is considered ep - pin 55 under the body of the device. the actual power dissipation of the device is dependent on the o perating mode, the heat transfer characteristics of the boar d and layout and the operating voltage. see figure 22 and figure 23 for examples of power dissipation profiles of two common configurations. o peration above the maximum operating junction temperature results in a reduction in rel iability leading to malfunction or permanent damage to the device. 9. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 10. nxp?s package reflow capability meets pb-f ree requirements for jedec standard j-std-020c. for peak package reflow temperature a nd moisture sensitivity levels (msl), go to www.nxp.com, search by part number [e.g. remo ve prefixes/suffixes and enter the core i d to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. table 3. maximum ratings (continued) all voltages are with respect to v ss unless otherwise noted. exceeding these ratings ma y cause a malfunction or permanent damage to the device. symbol ratings value unit notes
nxp semiconductors 9 34gd3000 4.2 static electrical characteristics table 4. static electrical characteristics characteristics noted under conditions 8.0 v v pwr = v sup 48 v , - 20 c t a 105 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes power inputs v pwr_st vpwr supply voltage startup threshold ?6.08.0v (11) i sup vsup supply current, v pwr = v sup = 48 v ? rst and enable = 5.0 v ? no output loads on gate drive pins, no pwm ? no output loads on gate drive pins, 20 khz, 50% duty cycle ? ? 1.0 ? ? 10 ma i pwr_on vpwr supply current, v pwr = v sup = 48 v ? rst and enable = 5.0 v ? no output loads on gate drive pi ns, no pwm, outputs initialized ? output loads = 620 nc per fet, 20 khz pwm ? ? 11 ? 20 95 ma (12) i sup i pwr sleep state supply current, rst = 0 v ?v sup = 48 v ?v pwr = 48 v ? ? 14 56 30 110 a v gatess sleep state output gate voltage ? ig < 100 a ??1.3v v boot trickle charge pump (bootstrap voltage) ?v sup = 14 v 22 28 32 v v f bootstrap diode forward voltage at 10 ma ??1.2v vdd internal regulator v dd v dd output voltage, v pwr = 8.0 v to 48 v, c = 0.47 f ? external load i dd_ext = 0 ma to 1.0 ma 4.5?5.5v (13) i dd internal v dd supply current, v dd = 5.5 v, no external load ??12ma vls regulator i peak peak output current, v pwr = 16 v, v ls = 10 v 350 600 800 ma v ls linear regulator output voltage, i vls = 0 ma to 60 ma, v pwr > v ls + 2.0 v 13.5 15 17 v (14) v thvls vls disable threshold (15) 7.5 8.0 8.5 v notes 11. operation with the charge pump is recommended when minimum system voltage could be less than 14 v.v pwr must exceed this threshold in order for the charge pump and v dd regulator to startup and drive v pwr to > 8.0 v. once v pwr exceeds 8.0 v, the circuits continues to operate even if system voltage drops below 6.0 v. 12. this parameter is guaranteed by design. it is not production tested. 13. minimum external capacitor for stable v dd operation is 0.47 f. 14. recommended external capacitor for the v ls regulator is 2.2 f low esr at each pin vls and vls_cap. 15. when v ls is less than this value, the outputs are disabled and holdoff ci rcuits are active. recovery requires initialization when v ls rises above this threshold again. a filter delay of approximately 700 ns on the comparator output eliminates responses to spuri ous transients on v ls .
10 nxp semiconductors 34gd3000 charge pump r ds(on)_hs r ds(on)_ls v threg charge pump ? high-side switch on resistance ? low-side switch on resistance ? regulation threshold difference ? ? 250 6.0 5.0 500 10 9.4 900 mv (16) , (18) v cp charge pump output voltage ?i out = 40 ma, 6.0 v < v sys < 8.0 v ?i out = 40 ma, v sys > = 8.0 v 8.5 12 9.5 ? ? ? v (17) , (18) gate drive r ds(on)_h_src high-side driver on resistance (sourcing) ?v pwr = v sup = 16 v, - 20 c t a 25 c ?v pwr = v sup = 16 v, 25 c < t a 105 c ? ? ? ? 6.0 8.5 r ds(on)_h_sink high-side driver on resistance (sinking) ?v pwr = v sup = 16 v ??3.0 i hs_inj high-side current injection allowed without malfunction ??0.5a (18) , (19) r ds(on)_l_src low-side driver on resistance (sourcing) ?v pwr = v sup = 16 v, - 20 c t a 25 c ?v pwr = v sup = 16 v, 25 c < t a 105 c ? ? ? ? 6.0 8.5 r ds(on)_l_sink low-side driver on-resistance (sinking) ?v pwr = v sup = 16 v ??3.0 i ls_inj low-side current injection allowed without malfunction ??0.5 (18) , (19) v gs_h v gs_l gate source voltage, v pwr = v sup = 48 v ? high-side, i gate = 0 ? low-side, i gate = 0 13 13 14.8 15.4 16.5 17 v (20) v hs_g_hold reverse high-side gate holding voltage gate output holding current = 2.0 a gate output holding current = 5.0 a, v sup < 26 v gate output holding current = 5.0 a, v sup < 48 v ? ? ? 10 10 ? 15 15 15 v (21) notes 16. when v ls is this amount below the normal v ls linear regulation threshold, the charge pump is enabled. 17. v sys is the system voltage on the input to the charge pump. recommended external components: 1.0 f mlc, mur 120 diode. 18. this parameter is a design char acteristic, not production tested. 19. current injection only occurs during outpu t switch transitions. the ic is immune to specified injected currents for a durati on of approximately 1.0 s after an output switch transition. 1.0 s is sufficient for all int ended applications of this ic. 20. if a slightly higher gate voltage is required, larger bootst rap capacitors are required. at high duty cycles, the bootstrap voltage may not recover completely, leading to a higher output on-resistance. this effect can be minimized by using lo w esr capacitors for the bootstra p and the vls capacitors. 21. high-side gate holding voltage is the voltage between the gate and source of the high-side fet when held in an on condition. the trickle charge pump supplies bias and holding current for t he high-side fet gate driver and output to maintain voltages after bootstrap events . this parameter is a design characteristic, not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 48 v , - 20 c t a 105 c, unless otherwise not ed. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
nxp semiconductors 11 34gd3000 overcurrent comparator v cm common mode input range 2.0 ? v dd -0.02 v (23) v os_oc input offset voltage -50 ? 50 mv v oc_hyst overcurrent comparator threshold hysteresis 50 300 mv (22) v oh v ol output voltage ? high level at i oh = -500 a ? low level at i ol = 500 a 0.85 v dd ? ? ? v dd 0.5 v hold off circuit i hold hold off current (at each gate pin) ?3.0 v < v sup < 48 v, v gate = 1.0 v 10 ? 300 a (24) phase comparator v ih_th high level input voltage threshold 0.5 v sup ? 0.65 v sup v v il_th low level input voltage threshold 0.3 v sup ? 0.45 v sup v v oh high level output voltage at i oh = -500 a 0.85 v dd ?v dd v v ol low level output voltage at i ol = 500 a ??0.5v r in high-side source input resistance ? 40 ? k (22) , (27) desaturation detector v des_th desaturation detector threshold 1.2 1.4 1.6 v (25) current sense amplifier r s recommended external series resistor (see figure 9 ) ?1.0?k r fb recommended external feedback resistor (see figure 9 ) ? limited by the output voltage dynamic range 5.0 ? 15 k (28) v id maximum input differential voltage (see figure 9 ) ?v id = v amp_p - v amp_n -800 ? 800 mv v cm input common mode range -0.5 ? 3.0 v (22) , (26) v os input offset voltage ?r s = 1.0 k , v cm = 0.0 v -15 ? 15 mv v os / t input offset voltage drift ?-10?v/c (22) notes 22. this parameter is a design char acteristic, not production tested. 23. as long as one input is in the common mode r ange there is no phase inversion on the output. 24. the hold off circuit is designed to oper ate over the full operating range of v sup . the specification indicates the conditions used in production test. hold off is activated at v por or v thvls. 25. desaturation is measured as the voltage drop below v sup , thus the threshold is compared to the dr ain-source voltage of the external high-side fet. see figure 5 . 26. as long as one input is within v cm the output is guaranteed to have the correct phase. exceeding the common mode rails on one input does not cause a phase inversion on the output. 27. input resistance is impedance from the high-side source and is referenced to v ss . approximate tolerance is 20 %. 28. the current sense amplifier is unity gain stable with a phase margin of approximately 45. see figure 10 . table 4. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 48 v , - 20 c t a 105 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
12 nxp semiconductors 34gd3000 current sense amplifier (continued) i b input bias current ?v cm = 2.0 v -200 ? +200 na i os input offset current ?i os = i amp_p - i amp_n -80 ? +80 na i os / t input offset current drift ?40?pa/c (29) v oh v ol output voltage ? high level with r load = 10 k to v ss ? low level with r load = 10 k to v dd v dd -0.2 ? ? ? v dd 0.2 v r i differential input resistance 1.0 ? ? m i sc output short-circuit current 5.0 ? ? ma c i common mode input capacitance at 10 khz ? ? 10 pf (29) , (30) cmrr common mode rejection ratio at dc ? cmrr = 20*log ((v out_diff /v in _ diff ) * (v in _ cm /v out _ cm )) 60 80 ? db a ol large signal open loop voltage gain (dc) ?78?db (29) , (30) nl nonlinearity ?r l = 1.0 k , c l = 500 pf, 0.3 < v o < 4.8 v, gain = 5.0 to 15 -1.0 ? +1.0 % (29) , (30) supervisory and control circuits v ih v il logic inputs (px_ls, px_hs, en1, en2) ? high level input voltage threshold ? low level input voltage threshold 2.1 ? ? ? ? 0.9 v (32) v ih v il logic inputs (si, sclk, cs ) ? high level input voltage threshold ? low level input voltage threshold 2.1 ? ? ? ? 0.9 v (31) , (32) v ihys input logic threshold hysteresis ? inputs px_ls, si, sclk, cs , px_hs, en1, en2 100 250 450 mv (31) i inpd input pull-down current, (px_ls, si, sclk, en1, en2) ?0.3 v dd v in v dd 8.0 ? 18 a notes 29. this parameter is a design char acteristic, not production tested. 30. without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. 31. this parameter is guaranteed by design, not production tested. 32. logic threshold voltages der ived relative to a 3.3 v 10% system. table 4. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 48 v , - 20 c t a 105 c, unless otherwise not ed. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
nxp semiconductors 13 34gd3000 supervisory and control circuits (continued) i inpu input pull-up current, (cs, px_hs) ?0 v in 0.7 v dd 10 ? 25 a (34) c in input capacitance ?0.0 v v in 5.5 v ?15?pf (33) v th_rst rst threshold 1.0?2.1v (35) r rst rst pull-down resistance ?0.3 v dd v in v dd 40 60 85 k v por power-off rst threshold, (v dd falling) 3.4 4.0 4.5 v v soh so high level output voltage ?i oh = 1.0 ma 0.9 v dd ??v v sol so low level output voltage ?i ol = 1.0 ma ? ? 0.1 v dd v i so_leak_t so tri-state leakage current ? cs = 0.7 v dd , 0.3 v dd v so 0.7 v dd -1.0 ? 1.0 a c so_t so tri-state capacitance ?0.0 v v in 5.5 v ?15?pf (33) , (36) v oh int high level output voltage ?i oh = -500 a 0.85 v dd ?v dd v v ol int low level output voltage ?i ol = 500 a ??0.5v thermal warning t warn thermal warning temperature 150 170 185 c (33) , (37) t hyst thermal hysteresis 8.0 10 12 c (33) notes 33. this parameter is guaranteed by design, not production tested. 34. pull-up circuits does not allow back biasing of v dd. 35. there are two elements in the rst circuit: 1) one generally lo wer threshold enables the internal regulator; 2) the second re moves the reset from the internal logic. 36. this parameter applies to the off state (tri-stated) conditi on of so is guaranteed by design but is not production tested. 37. the thermal warning circuit does not force ic shutdown above th is temperature. it is possible to set a bit in the mask regis ter to generate an interrupt when overtemperature is detected, and the status bit al ways indicates if any of the three individual thermal warning circuits in the ic sense a fault. table 4. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 48 v , - 20 c t a 105 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
14 nxp semiconductors 34gd3000 4.3 dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 8.0 v v pwr = v sup 48 v, - 20 c t a 105 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes internal regulators t pu_vdd v dd power-up time (until int high) ?8.0 v v pwr ? ? 2.0 ms (38) , (45) t pu_vls vls power-up time ?16 v v pwr ? ? 2.0 ms (39) , (45) charge pump f osc charge pump oscillator frequency 90 125 190 khz sr cp charge pump slew rate ? 100 ? v/s (40) gate drive t onh high-side turn on time ? transition time from 1.0 v to 10 v, load: c = 500 pf, r g = 0, ( figure 7 ) ? 20 35 ns (41) t d_onh high-side turn on delay ? delay from command to 1.0 v, ( figure 7 ) 130 265 386 ns (42) t offh high-side turn off time ? transition time from 10 v to 1.0 v, load: c = 500 pf, r g = 0, ( figure 8 ) ? 20 35 ns (41) t d_offh high-side turn off delay ? delay from command to 10 v, ( figure 8 ) 130 265 386 ns (42) t onl low-side turn on time ? transition time from 1.0 v to 10 v, load: c = 500 pf, r g = 0, ( figure 7 ) ? 20 35 ns (41) t d_onl low-side turn on delay ? delay from command to 1.0 v, ( figure 7 ) 130 265 386 ns (42) t offl low-side turn off time ? transition time from 10 v to 1.0 v, load: c = 500 pf, r g = 0, ( figure 8 ) ? 20 35 ns (41) t d_offl low-side turn off delay ? delay from command to 10 v, ( figure 8 ) 130 265 386 ns (42) t d_diff same phase command delay match -20 0.0 +20 ns (43) t dur thermal filter duration 8.0 ? 30 s (44) notes 38. the power-up time of the ic depends in part on the time requir ed for this regulator to charge up the external filter capacit or on v dd . 39. the power-up time of the ic depends in part on the time requir ed for this regulator to charge up the external filter capacit ors on vls and vls_cap. this delay includes t he expected time for v dd to rise. 40. the charge pump operating at 12 v v sys , 1.0 f pump capacitor, mur120 diodes and 47 f filter capacitor. 41. this parameter is guaranteed by characterization, not production tested. 42. these delays include all logic delays exce pt deadtime. all internal l ogic is synchronous with the internal clock. the total delay includes one clock period for state machine decision block, an additional clock period for fullon mux l ogic, input synchronization time and output driver propagation delay. subtract one clock period for operation in fullon mode wh ich bypasses the state machine decision block. synchronization time accounts for up to one clock period of variation. see figure 6 . 43. the maximum separation or overlap of the high and low-side gate drives, due to propagation delays when commanding one on and the other off simultaneously, is guaranteed by design. 44. the output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt. 45. this specification is based on capacitance of 0.47 f on vdd, 2.2 f on vls and 2.2 f on vls_cap.
nxp semiconductors 15 34gd3000 gate drive (continued) t dc duty cycle 0.0 ? 96 % (46) , (47) t dc 100% duty cycle duration ? ? unlimited s (46) , (47) t max maximum programmable deadtime 10.2 15 19.6 s (48) overcurrent comparator t oc overcurrent protection filter time 0.9 ? 3.5 s t roc rise time (oc_out) ? 10% - 90% ?c l = 100 pf 10 ? 240 ns t foc fall time (oc_out) ? 90% - 10% ?c l = 100 pf 10 ? 200 ns desaturation detector and phase comparator t r t f phase comparator propagation delay time to 50% of v dd ; c l 100 pf ? rising edge delay ? falling edge delay ? ? ? ? 200 350 ns t match phase comparator match (prop delay mismatch of three phases) ?c l = 100 pf ? ? 100 ns (46) t blank desaturation and phase error blanking time 4.7 7.1 9.1 s (49) t filt desaturation filter time (f ilter time is digital) ? fault must be present for this time to trigger 640 937 1231 ns (46) current sense amplifier t settle output settle time to 99% ?r l = 1.0 k , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5 to 15 ? 1.0 2.0 s (46) , (50) t is_rise output rise time to 90% ?r l = 1.0 k , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5.0 to 15 ? ? 1.0 s (51) t is_fall output fall time to 10% ?r l = 1.0 k , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5.0 to 15 ? ? 1.0 s (51) sr 5 slew rate at gain = 5.0 ?r l = 1.0 k , c l = 20 pf 5.0 ? ? v/s (46) f m phase margin at gain = 5.0 ?30? (46) g bw unity gain bandwidth ?r l = 1.0 k , c l = 100 pf ?20?mhz (46) notes 46. this parameter is guaranteed by design, not production tested. 47. as duty cycle approaches the limit of 100% or 0% there is a maximum and minimum which is not achievable due to deadtime, pro pagation delays, switching times and charge time of the bootstrap capacitor (for t he high-side fet). 0% is availabl e by definition (fet always o ff) and unlimited on (100%) is possible as long as gate charge maintenanc e current is within the trickle charge pump capacity. 48. a minimum deadtime of 0.0 can be set via an spi command. when deadt ime is set via a deadtime command, a minimum of 1 clock c ycle duration and a maximum of 255 clock c ycles is set using the internal time base clock as a reference. commands exceeding this value limit s at this value. 49. blanking time, t blank , is applied to all phases simultaneously when switching on any output fet. this precludes false errors due to system noise during the switching event. 50. without considering any offset s such as input offset voltage, internal mism atch and assuming no tolerance error in external resistors. 51. rise and fall times are measured from the transition of a step function on the input to 90% of the change in output voltage. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 48 v, - 20 c t a 105 c, unless otherwise not ed. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
16 nxp semiconductors 34gd3000 current sense amplifier (continued) bw g bandwidth at gain = 15 ?r l = 1.0 k , c l = 50 pf 2.0 ? ? mhz (52) cmr common mode rejection (cmr) with v in ?v in_cm = 400 mv*sin(2* *freq*t) ?v in _ dif = 0.0 v, rs = 1.0 k ?r fb = 15 k , v refin = 0.0 v cmr = 20*log(v out /v in _ cm ) ? freq = 100 khz ? freq = 1.0 mhz ? freq = 10 mhz 50 40 30 ? ? ? ? ? ? db (52) supervisory and control circuits t prop en1 and en2 propagation delay ? ? 280 ns t rint int rise time cl = 100 pf 10 ? 250 ns t fint int fall time cl = 100 pf 10 ? 200 ns t propint int propagation time ? ? 250 ns t trrst rst transition time (rise and fall) ? ? 1.25 s (52) , (53) spi interface timing f op maximum frequency of spi operation ? 4.0 mhz f tb internal time base 13 17 25 mhz tc tb internal time base drift from value at 25 c -5.0 ? 5.0 % (54) t lead falling edge of cs to rising edge of sclk (required setup time) 100 ? ? ns (54) t lag falling edge of sclk to rising edge of cs (required setup time) 100 ? ? ns (54) t sisu si to falling edge of sclk (required setup time) 25 ? ? ns (54) t sihold falling edge of sclk to si (required setup time) 25 ? ? ns (54) t rsi si, cs, sclk signal rise time ? 5.0 ? ns (54) , (55) t fsi si, cs, sclk signal fall time ? 5.0 ? ns (54) , (55) t soen time from falling edge of cs to so low-impedance ? 55 100 ns (54) , (56) t sodis time from rising edge of cs to so high-impedance ? 100 125 ns (54) , (57) t valid time from rising edge of sclk to so data valid ? 80 125 ns (54) , (58) t dt time from rising edge of cs to falling edge of the next cs 200 ? ? ns (54) notes 52. this parameter is guaranteed by design, not production tested. 53. t trrst is given as a design guideline. the bounds for this specification are vpwr 58 v, total capacitance on vls > 1.0 f. 54. this parameter is guaranteed by design, not production tested. 55. rise and fall time of incoming si, cs, and sclk signals sugges ted for design consideration to prevent the occurrence of doub le pulsing. 56. time required for valid output status data to be available on so pin. 57. time required for output states data to be terminated at so pin. 58. time required to obtain valid data out from so following the rise of sclk with 200 pf load. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 48 v, - 20 c t a 105 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
nxp semiconductors 17 34gd3000 4.4 timing diagrams figure 4. spi interface timing figure 5. desaturation blanking and filtering detail figure 6. deadtime control delays t do (dis) 0.7 v dd 0. 2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t di(su) t di(ho ld) t valid t lag cs sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd t do(en) t sodis t soen t sisu t sihold t lag from delay timer p x _hs p x _ls desaturation fault p x _ls p x _hs en1 en2 rst state deadtime control 1 st pulse machine p x _hs_g p x _hs_s p x _ls_g dq clk d q clk dq clk dq clk dq clk dq clk b out a mux b out a mux
18 nxp semiconductors 34gd3000 figure 7. driver turn-o n time and turn-on delay figure 8. driver turn-o ff time and turn-off delay 50 % px_hs _g px_hs 10v 1.0v t d_onh t onh 50% px_ls_g px_ls 10v 1.0v t d_onl t onl 50% 10v 1.0v t d_offl t offl px_ls_g px_ ls px_hs_g px_hs 50% 10v 1.0v t d_offh t offh
nxp semiconductors 19 34gd3000 figure 9. current amplifier and input waveform (v in voltage across r sense ) figure 10. typical amplifier open-loop gain and phase vs. frequency v in - ref r sense amp_out amp_p amp_n oc_th v id r f bn r fb p r s r s + + - to protection circuits 0v 0v -400mv to + 400mv -400mv to + 400mv 0.5s - 50s 0.5s - 50s 0s - 0.5s gain (db) phase (degrees) gain phase
20 nxp semiconductors 34gd3000 5 functional descriptions 5.1 introduction the 34gd3000 provides an interface between an mcu and the exter nal fets used to drive three phase motors. a typical external fe t may have an on resistance of 4.0 m or less and could require a gate charge of over 40 0 nc to fully turn on. the ic can operate in 12 v to 48 v environments. there are many methods for cont rolling three phase motor systems, so the ic enforces few constrai nts in driving the fets. the 3 4gd3000 does however provide deadtime (cross-over) blanking and logic in or der to protect the external fets. under special configuratio ns, both of these features can be overridden, allowing both fets in a phase to be simultaneously enabled. an spi port is used to configure the 34gd3000?s modes. 5.2 functional pin description 5.2.1 phase a (phasea) this pin is the totem pole output of the phase a comparator. this output is low when the voltage on phase a high-side source (s ource of the high-side load fet) is less than 50 percent of v sup . 5.2.2 power ground (pgnd) this pin is power ground for the charge pump. it should be connec ted to vss, however routing to a single point ground on the pc b may help to isolate charge pump noise. 5.2.3 enable 1 and enable 2 (en1, en2) both of these logic signal inputs must be high to enable any gate drive output. when either or both are low, the internal logic (spi port, etc.) still functions normally, but all gate drives are forced off (external power fet gates pulled low). the signal is asynchr onous. when en1 and en2 return high to enable the outputs, each ls driver must be pulsed on before the corresponding hs driver can be commanded on. this ensures the bootstrap capacitors are charged. see initialization requirements on page 39 . 5.2.4 reset (rst) when the reset pin is low the integrated circuit (ic) is in a lo w-power state. in this mode all outputs are disabled, internal bias circuits are turned off, and a small pull-down current is applied to the output gate drives. the internal logic resets within 77 ns of reset going low. when rst is low, the ic consumes minimal current. 5.2.5 charge pump out (pump) this pin is the switching node of the charge pump circuit. t he output of the internal charge pump support circuit. when the cha rge pump is used, it is connected to the external pumping capacitor. this pin may be left floating if the charge pump is not required. 5.2.6 charge pump input (vpump) this pin is the input supply for the charge pump circuit. when t he charge pump is required, this pin should be connected to a p olarity protected supply. this input should never be connected to a supply greater than 40 v. if the charge pump is not required this p in may be left floating. 5.2.7 vsup input (vsup) the supply voltage pin should be connected to the common connection of the high-side fets. it is the reference bias for the pha se comparators and desaturation comparator. it is also used to prov ide power to the internal steady state trickle charge pump and to energize the hold off circuit.
nxp semiconductors 21 34gd3000 5.2.8 phase b (phaseb) this pin is the totem pole output of the phase b comparator. this output is low when the voltage on phase b high-side source (s ource of the high-side load fet) is less than 50 percent of v sup . 5.2.9 phase c (phasec) this pin is the totem pole output of the phase c comparator. th is output is low when the voltage on phase c high-side source (s ource of the high-side load fet) is less than 50 percent of v sup . 5.2.10 phase a high-side input (pa_hs) this input logic signal pin enables the high-side driver for phase a. the signal is active low and is pulled up by an internal current source. 5.2.11 phase a low-side input (pa_ls) this input logic signal pin enables the low-side driver for phase a. the signal is active high and is pulled down by an interna l current sink. 5.2.12 vdd voltage regulator (vdd) vdd is an internally generated 5.0 v supply. the internal regulator provides continuous power to the ic and is a supply referen ce for the spi port. a 0.47 f (min) decoupling capacitor must be connected to this pin. this regulator is intended for internal ic use an d can supply only a small (1.0 ma) external load current. a power-on-reset (por) circuit monitors this pin and until the voltage rises above the threshold, the internal logic is reset; driver outputs is tri-stated and spi communication disabled. the vdd regulator ca n be disabled by asserting the rst signal low. the vdd regula tor is powered from the vpwr pin. 5.2.13 phase b high-side control input (pb_hs) this pin is the input logic signal, enabling the high-side driver for phase b. the signal is active low, and is pulled up by an internal current source. 5.2.14 phase b low-si de input (pb_ls) this pin is the input logic signal, enabling the low-side driver for phase b. the signal is active high, and is pulled down by an internal current sink. 5.2.15 interrupt (int) the interrupt pin is a totem pole logic output. when a fault is detected, this pin pulls high until it is cleared by executing the clear interrupt command via the spi port. the faults capable of causing an interrupt can be masked via the mask0 and mask1 spi regist ers to customize the response. 5.2.16 chip select ( cs ) chip select is a logic input which frames the spi commands and enables the spi port. this signal is active low, and is pulled u p by an internal current source. 5.2.17 serial in (si) the serial in pin is used to input data to the spi port. clocke d on the falling edge of sclk, it is the most significant bit (m sb) first. this pin is pulled down by an internal current sink. 5.2.18 serial clock (sclk) this logic input is the clock is used for the spi port. the sclk typically runs at 3.0 mhz (up to 5.0 mhz) and is pulled down b y an internal current sink.
22 nxp semiconductors 34gd3000 5.2.19 serial out (so) output data for the spi port streams from this pin. it is tr i-stated until cs is low. new data appears on rising edges of sclk in preparation for latching by the falling edge of sclk on the master. 5.2.20 phase c low-side input (pc_ls) this input logic pin enables the low-side driver for phase c. this pin is an active high, and is pulled down by an internal cur rent sink. 5.2.21 phase c high-side input (pc_hs) this input logic pin enables the high-side driver for phase c. this signal is active low, and is pulled up by an internal curre nt source. 5.2.22 amplifier output (amp_out) this pin is the output for the current sensing amplifier. it is also the sense input to the overcurrent comparator. 5.2.23 amplifier inve rting input (amp_n) the inverting input to the current sensing amplifier. 5.2.24 amplifier non-inverting input (amp_p) the non-inverting input to the current sensing amplifier. 5.2.25 overcurrent comp arator output (oc_out) the overcurrent comparator output is a totem pole logic leve l output. a logic high indicates an overcurrent condition. 5.2.26 overcurrent compar ator threshold (oc_th) this input sets the threshold level of the overcurrent comparator. 5.2.27 voltage source supply (vss) vss is the ground reference for the logic interface and power supplies. 5.2.28 ground (gnd0,gnd1) these two pins are connected internally to vss by a 1.0 resistor. they provide device substrate connections and the primary return path for esd protection. 5.2.29 vls regulator capacitor (vls_cap) this connection is for a capacitor which provides a low-imped ance for switching currents on the gate drive. a low esr decouplin g capacitor, capable of sourcing the pulsed drive currents must be c onnected between this pin and vss. this is the same dc node a s vls, but it is physically placed on the opposite end of the ic to minimize the source impedance to the gate drive circuits. 5.2.30 phase c low-side source (pc_ls_s) the phase c low-side source is the pin used to return the gate currents from the low-side fet. best performance is realized by connecting this node directly to the source of the low-side fet for phase c. 5.2.31 phase c low-side gate (pc_ls_g) this is the gate drive for the phase c low-side output fet. it provides high-current through a low-impedance to turn on and off the low- side fet. a low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to f low in the external fet. this output has also been designed to resist the influence of negative currents.
nxp semiconductors 23 34gd3000 5.2.32 phase c high-side source (pc_hs_s) the source connection for the phase c high-side output fet is th e reference voltage for the gate drive on the high-side fet and also the low-voltage end of the bootstrap capacitor. 5.2.33 phase c high-s ide gate (pc_hs_g) this is the gate drive for the phase c high-side output fet. this pin provides the gate bias to turn the external fet on or off . the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do no t overcome an off-state driver and allow pulses of current to flow in the external fets. this output has also been designed to re sist the influence of negative currents. 5.2.34 phase c bootstrap (pc_boot) this is the bootstrap capacitor connection for phase c. a capaci tor connected between pc_hs_s and this pin provides the gate vo ltage and current to drive the external fet gate. typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance . the voltage across this capacitor is limited to about 15 v. 5.2.35 phase b low-side source (pb_ls_s) the phase b low-side source is the pin used to return the gate cu rrents from the low-side fet. best performance is realized by connecting this node directly to the source of the low-side fet for phase b. 5.2.36 phase b low-side gate (pc_ls_g) this is the gate drive for the phase b low-side output fet. it provides high-current through a low-impedance to turn on and off the low- side fet. a low-impedance drive ensures transient currents do not ov ercome an off-state driver and allow pulses of current to f low in the external fet. this output has also been designed to resist the influence of negative currents. 5.2.37 phase b high-side source (pb_hs_s) the source connection for the phase b high-side output fet is the reference voltage for the gate drive on the high-side fet and also the low-voltage end of the bootstrap capacitor. 5.2.38 phase b high-s ide gate (pb_hs_g) this is the gate drive for the phase b high-side output fet. this pin provides the gate bias to turn the external fet on or off . the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do no t overcome an off-state driver and allow pulses of current to flow in the external fets. this output has also been designed to re sist the influence of negative currents. 5.2.39 phase b bootstrap (pb_boot) this is the bootstrap capacitor connection for phase b. a capacitor connected between pc_hs_s and this pin provides the gate vo ltage and current to drive the external fet gate. typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance . the voltage across this capacitor is limited to about 15 v. 5.2.40 phase a low-side source (pa_ls_s) the phase a low-side source is the pin used to return the gate cu rrents from the low-side fet. best performance is realized by connecting this node directly to the source of the low-side fet for phase a. 5.2.41 phase a low-side gate (pa_ls_g) this is the gate drive for the phase a low-side output fet. it provides high-current through a low-impedance to turn on and off the low- side fet. a low-impedance drive ensures transient currents do not ov ercome an off-state driver and allow pulses of current to f low in the external fet. this output has also been designed to resist the influence of negative currents.
24 nxp semiconductors 34gd3000 5.2.42 phase a high-side source (pa_hs_s) the source connection for the phase a high-side output fet is t he reference voltage for the gate drive on the high-side fet and the low- voltage end of the bootstrap capacitor. 5.2.43 phase a high-side gate (pa_hs_g) this is the gate drive for the phase a high-side output fet. this pin provides the gate bias to turn the external fet on or off . the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do no t overcome an off-state driver and allow pulses of current to flow in the external fets. this output was designed to resist the influence of negative currents. 5.2.44 phase a bootstrap (pa_boot) this is the bootstrap capacitor connection for phase a. a capacitor connected between pc_hs_s and this pin provides the gate vo ltage and current to drive the external fet gate. typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance . the voltage across this capacitor is limited to about 15 v. 5.2.45 vls regulator (vls) vls is the gate drive power supply regulated at approximately 15 v. this is an internally generated supply from v pwr . it is the source for the low-side gate drive voltage, and also the high-side bootstra p source. a low esr decoupling capacitor, capable of sourcing t he pulsed drive currents, must be connec ted between this pin and vss. 5.2.46 vpwr input (vpwr) vpwr is the power supply input for v ls and v dd . current flowing into this input recharges the bootstrap capacitors as well as supplying power to the low-side gate drivers and the v dd regulator. an internal regulator regulates the actual gate voltages. this pin can be connected to system supply voltage if power dissipation is not a concern. 5.2.47 exposed pad (ep) the primary function of the exposed pad is to conduct heat out of the device. this pad may be connected electrically to the sub strate of the device.the device performs as specified with the exposed p ad un-terminated (floating). however, it is recommended the expos ed pad be terminated to pin 29 (vss) and the system ground.
nxp semiconductors 25 34gd3000 6 functional internal block description figure 11. functional internal block description all functions of the ic can be described as the following five major functional blocks: ? logic inputs and control ? integrated supply ? high-side and low-side drivers ? sensing and protection 6.1 logic inputs and control this section contains the spi port, control logic, and shoot-th rough timers. the ic logic inputs have schmitt trigger inputs wi th hysteresis. logic inputs are 3.3 v compatible. the logic outputs are driven from the internal supply of approximately 5.0 v. the spi regist ers and functionality is described completely in the logic commands and registers section of this document. spi functionality includes the following: ? programming of deadtime delay ?this delay is adjustable in approximately 50 ns st eps from 0 ns to 12 s. calibration of the delay, because of internal ic variations, is performed via the spi. ? enabling of simultaneous operation of high-side and low-side fets ?normally, both fets would not be enabled simultaneously. however, for certain applications where the load is connected bet ween the high-side and low-side fets, this could be advantageo us. if this mode is enabled, the blanking time delay is disabled. a sequence of commands may be required to enable this function to prevent inadvertent enabling. in addition, this command can only be executed once after reset to enable or disable simultaneous turn-on . ? setting of various operating modes of the ic and enabling of interrupt sources. the 34gd3000 allows different operating modes to be set and locked by an spi command (fullon, desaturation fault, zero deadtime ). spi commands can also determine how the various faults are reported. 34gd3000 - functional block diagram integrated supply sensing & protection drivers high-side and low-side output pre-drivers logic & control integrated supply trickle charge pump 5.0 v regulator vls regulator main charge pump sensing & protection hold-off temperature current sense overcurrent de-sat phase undervoltage logic & control dead time fault register mode control phase control spi communication
26 nxp semiconductors 34gd3000 ? read back of internal registers . the status of the 34gd3000 status registers can be read back by the master (dsp or mcu). the px_hs and px_ls logic inputs are edge sensitive. this means the leading edge on an input causes the complementary output to immediately turn off and the selected one to turn on after the deadtime delay as illustrated in figure 12 . the deadtime delay timer always starts at the time a fet is commanded off and prevents the complementary fet from being command ed on until after the deadtime has elapsed. commands to turn on t he complementary fet after the deadtime has elapsed are executed immediately without any further delay (see figure 6 and figure 12 ). figure 12. edge sensitive logic inputs (phase a) 6.1.1 low-side and bootstrap supply (vls) this is the portion of the ic providing current to recharge t he bootstrap capacitors. it also supplies the peak currents requir ed for the low- side gate drivers. the power for the gate drive circuits is provi ded by vls which is supplied from the vpwr pin. this pin can b e connected to system supply voltage and is capable of withstanding up to the full transient voltage of the system. however, the ic only re quires a low- voltage supply on this pin, typically 13 to 16 v. higher voltages on this pin increases the ic power dissipation. in 12 v systems the supply voltage can fall as low as 6.0 v. th is limits the gate voltage capable of being applied to the fets and reduces system performance due to the higher fet on-resistance. to allow a higher gate voltage to be supplied, the ic also incorporates a charge pump. the switches and control circuitry are intern al; the capacitors and diodes are external (see figure 21 ). 6.1.2 low-side drivers these three drivers turn on and off the external low-side fets . the circuits provide a low-impedance drive to the gate, ensurin g the fets remain off in the presence of high dv/dt transients on their dr ains. additionally, these output drivers isolate the other porti ons of the ic from currents capable of being injected into the subs trate due to rapid dv/dt transients on the fet drains. low-side drivers switch power from vls to the gates of the low- side fets. the low-side drivers ar e capable of providing a typic al peak current of 2.0 a. this gate drive current may be limited by exte rnal resistors in order to achieve a good trade-off between the efficiency and emc (electro-magnetic compatibility) compliance of the applicatio n. the low-side driver uses high-side pmos for turn on and low- side isolated ldmos for turn off. the circuit ensures the impedance of the driver remains low, even during periods of reduced c urrent. current limit is blanked immediately after subsequent input stat e change in order to ensure device stays off during dv/dt trans ients. 6.1.3 high-side drivers these three drivers switch the voltage across the bootstrap capacitor to the external high-side fets. the circuits provide a lo w-impedance drive to the gate, ensuring the fets remain off in the presence of high dv/dt transients on their sources. further, these outpu t drivers isolate the other portions of the ic from currents capable of being injected into the substrate due to rapid dv/dt transients o n the fets. the high-side drivers deliver power from t heir bootstrap capacitor to the gate of the external high-side fet, thus turning the high-side fet on. the high-side driver uses a level shifter, which allows the gate of the external high-side fet to be turned off by switchin g to the high- side fet source. pa _h s pa_ls pa_ h s_ g pa_ls_g de adt ime de lay
nxp semiconductors 27 34gd3000 the gate supply voltage for the high-side drivers is obtained from the bootstrap supply, so, a short time is required after the application of power to the ic to charge the bootstrap capacitors. to ensure this occurrence, the internal control logic does not allow a high -side switch to be turned on after entering the enable state until the corresponding low-side switch is enabled at least once. caution must be exercised after a long period of inactivity of the low-side switches to verify the bootstrap capacitor is not discharged. it is charged b y activating the low-side switches for a brief period, or by attaching external bleed resistors from the hs_s pins to gnd. see initialization requirements on page 39 . to achieve a 100% duty cycle operat ion of the high-side external fets, a fully in tegrated trickle charge pump provides the char ge necessary to maintain the external fet gates at fully enhanced levels. the trickle charge pump has limited ability to supply ex ternal leakage paths while performing it?s primary function. these limits are based on maintaining the voltage at cboot at least 3.0 v greater than the voltage on the hs_s for this phase. if this voltage differential becomes less than 3.0 v, the corresponding high-side fet most likely does not remain fully enhanced and the high-side driver may malfunction due to insufficient bias voltage between cboot a nd hs_s. the slew rate of the external output fet is limited by the driver output impedance, overall (external and internal) gate resist ance and the load capacitance. to ensure the low-side fet is not turned on by a large positive dv/dt on the drain of the low-side fet, the t urn-on slew rate of the high-side should be limited. if the slew rate of the high-side is limited by the gate-drain capacitance of the high -side fet, then the displacement current injected into the low-side gate drive out put is approximately the same value. therefore, to ensure the low-side drivers can be held off, the voltage drop across the low-side gate driver must be lower than the threshold voltage of the low-s ide fet (see figure 13 ). similarly, during large negative dv/dt, the high-side fet is able to remain off if its gate drive low-side switch, develops a v oltage drop less than the threshold voltage of the high-side fet. the gate drive low-side switch discharges the gate to the source. additionally, during negative dv/dt the low-side gate drive could be forced below ground. the low-side fets must not inject det rimental substrate currents in this condition. the occurrence of these cases depends on the polarity of the load current during switchin g. figure 13. positive dv/dt transient 6.1.4 driver fault protection the 34gd3000 ic integrates several protection mechanisms against various faults. the first of them is the current sense amplifi er with the overcurrent comparator. these two blo cks are common for all three driver phases. phase x output phase return px_ls_s px_ls_g px_hs_s low -si de driver ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage dv/dt c gs c dg c ds r g i cdg vls 33927 + - g s d di scr ete fet package z o 34gd3000
28 nxp semiconductors 34gd3000 6.1.4.1 current sense amplifier this amplifier is usually connected as a differential amplifier (see figure 9 ). it senses a current flowing through the external fets as a voltage across the current sense resistor r sense . since the amplifier common mode range does not extend below ground, it is necessary to use an external reference to permit m easuring both positive and negative currents. the amplifier output can be monitored dir ectly (e.g. by the microcontroller?s adc) at the amp_out pin, providing the means for closed loop control with the 34gd3000. the output vol tage is internally compared with the overcurrent comparator threshold voltage (see figure 21 ). 6.1.4.2 overcurrent comparator the amplified voltage across r sense is compared with the pre-set threshold value by the overcurrent comparator input. if the current sense amplifier output voltage exceeds the threshold of the overcu rrent comparator, it would change the status of its output (o c_out pin) and the fault condition would be latched (see 7.2.3.2 figure 17 ). the occurrence of this fault would be signalled by the return va lue of the status register 0. if the proper interrupt mask has been set, this fault condition generates an interrupt - the int pin is asserted high. the int is held in the high state until the fault is rem oved, and the appropriate bit in the status register 0 is cleared by the clin t0 command. this fault reporting technique is described in detai l in the logic commands and registers section. 6.1.4.3 desaturation detector the desaturation detector is a comparator integrated into the output driver of each phase chan nel. it provides an additional me ans to protect against ?short-to-ground? fault conditions. a short-to-ground is detected by an abnormally high-voltage drop in v ds of the high-side fet. note that if the gate-source voltage of the high-side fet drops below saturation, the device goes into linear mode of cond uction, which can cause a desaturation error. figure 14. short to ground detection v sup phase x output r sense phase return t-lim vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot phase comp. desat. comp. 3x + - vsup vsup 1.4v low -side dr iver hi gh -side dr iver hs control r r vls to current sense amplif. phase x output shorted to ground (low-side fet shorted) ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage shorted to ground correct phase x output voltage 0.5v sup phasex cor rec t fault phase error t blank t filt des aturation er r or
nxp semiconductors 29 34gd3000 when switching from low-side to high-side, the high-side is co mmanded on after the end of the deadtime. the deadtime period sta rts when the low-side is commanded off. if the voltage at px_hs_s is less than 1.4 v below v sup after the blanking time (t blank ), a desaturation fault initiates. an additional 1.0 s digital filter is applied from the initiation of the desaturation fault before it is registered, and all phase drivers are turned off (px_hs_g cl amped to px_hs_s and px_ls_g clamped to px_ls_s). if the desaturation fault conditi on clears before the filter time expires, the f ault is ignored and the filter timer resets. valid faults are registered in the fault st atus register, which can be retrieved by way of the spi. additional spi commands mas k the int flag and disable output stage shutdown, due to desaturation and phase errors. see the logic commands and registers section for details on masking int behavior and disabling the protective function. figure 15. short to supply detection 6.1.4.4 phase comparator faults could also be detected as phase errors . a phase error is generated if the output sig nal (at px_hs_s) does not properly reflect the drive conditions. a phase error is detected by a phase comparat or. the phase comparator compares the voltage at the px_hs_s nod e with a reference of one half the voltage at the vsup pin. a high-side phase error (which triggers the desaturation detector) oc curs when the high-side fet is commanded on, and px_hs_s is still low at the end of the deadtime and blanking time duration. similarly, a ls phase error occurs when the low-side fet is commanded on, and the px_hs_s is still high at the end of the deadtime and blanking time duration. the phase error flag is the triple or of phase errors from each phase. each phase error is the or of the high-side and low-side phase errors. this flag can generate an interrupt if the appropriate ma sk bit is set. the int is held in the high state until the fau lt is removed, and the appropriate bit in the status register 0 is cleared by the clint1 command. this fault reporting mechanism is described in d etail in the logic commands and registers section. v sup phase x output r sense phase return t-lim vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_b oot phase comp. desat. comp. 3x + - vsup vsup 1. 4v low -side driver hi gh -side driver hs control r r vls to current sense amplif. phase x output shortedtov sup (high-side fet shorted) ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage shorted to v sup correct phase x output voltage 0.5v sup phase x correct fault phase error t blank
30 nxp semiconductors 34gd3000 6.1.4.5 v ls undervoltage since v ls supplies both the gate driver circuits and the gate voltage, it is critical it maintains sufficient potential to place the pow er stage fets in saturation. since proper operation cannot continue with insufficient levels, a low v ls condition shuts down driver operation. the v ls undervoltage threshold is between 7.5 v and 8.5 v. when a decreasing level reaches the threshold, both the hs and the ls outpu t gate circuit drive the gates off for about 8.0 s before reducing the drive to hold off levels. since a low v ls is a condition for turning on the hold off circuit, hold off then provides a weak pull-down on all gates. a filter timeout of about 700 ns insures noise on v ls does not cause premature protective action. when v ls rises above this threshold again, the ls gate immediately follows the level of the input. however, a short initialization sequ ence must be executed to restore operation of the hs gate (see initialization requirements on page 39 ). since v ls is no longer undervoltage, the hold off circuit is turned off and the hs gate is in a high-i mpedance state until the ls gate responds to an input command to turn off. 6.1.4.6 hold off circuit the ic guarantees the output fets are turned off in the absence of v dd or v pwr by means of the hold off circuit. a small current source, generated from v sup , typically 100 a, is mirrored and pulls all the output gate drive pins low when v dd is less than about 3.0 v, rstb is active (low), or when v ls is lower than the vls_disable threshold. a minimum of 3.0 v is required on v sup to energize the hold off circuit. 6.1.4.7 charge pump the charge pump circuit provides the basic switching elements r equired to implement a charge pump, when combined with external capacitors and diodes for enhanced low-voltage operation. when the 34gd3000 is connected per the typical application using the charge pump (see figure 21 ), the regulation path for v ls includes the charge pump and a linear regulator. the regulation set point fo r the linear regulator is nominally at 15.34 v. as long as t he vls output voltage (vls out ) is greater than the v ls analog regulator threshold (vls ath ) minus v threg , the charge pump is not active. if vls out < vls ath ? v threg , the charge pump turns on until vls out > vls ath ? v threg + v hyst . v hyst is approximately 200 mv. vls ath does not interfere with this cycle even when there is overlap in the thresholds, due to the design of the regulator system. the maximum current the charge pump can supply is dependent on t he pump capacitor value and quality, the pump frequency (nomina lly 130 khz), and the r ds(on) of the pump fets. the effective charge voltage for the pump capacitor would be v sys ? 2 * v diode . the total charge transfer would then be c pump * (v sys ? 2*v diode ). multiplying by the switch frequency gives the theoretical current the pump can transfer: f pump * c pump * (v sys ? 2*v diode ). note: there is also another smaller, fully int egrated charge pump (trickle charge pump - see figure 2 ), which is used to maintain the high-side drivers? gate v gs in 100 percent duty cycle modes.
nxp semiconductors 31 34gd3000 7 functional device operation 7.1 operational modes 7.1.1 reset and enable the 34gd3000 has three power modes of operation, as described in table 6 . there are three global control inputs (rstb, en1, en2), which together with the status of vdd, vls, and desat/phase faults control the behavior of the ic. the operating status of the ic can be described by the following five modes: ? sleep mode - when rstb is low, the ic is in sleep mode. the current consumption of the ic is at minimum. ? standby mode - the rstb input is high while one of the enable inputs is low. the ic is fully biased and operating, all the external fets are actively turned off by both high-side and low-si de gate drives. the ic is ready to enter the enable mode. ? initialization mode - when en1, en2, and rstb all go high, the device enters the initialization mode. toggling the ls and then the hs initializes the driver and normal operation, the enable mode begins. ( initialization requirements on page 39 ). ? enable mode - after initialization is complete, the device goes into the enable mode and operates normally. normal operation continues in this mode as long as both enable pins and rstb are high. ? fault protection mode - if a protective fault occurs (either desat/phase or vls uv) the device enters a fault protection mode. after a fault clears, the device requires initialization again before resuming normal enable mode operation. table 6. functions of rstb, en1, and en2 pins rstb en1, en2 mode of operation (driver condition) 0xx sleep mode - in this mode (low quiescent current), the driver output stage is switched off with a weak pull-down. all error and spi registers are cleared. the internal 5.0 v regulator is turned off and v dd is pulled low. all logic out puts except so are clamped to v ss . 1 0x x0 standby mode - ic is fully biased and all functions are operating, the output drivers actively turn off all of the external fets (after initialization). the spi port is functional. logic level outputs are driven with low-impedance. so is high-impedance unless csb is low. v dd , charge pump, and v ls regulators are all operating. the ic is ready to move to enable mode. 111 initialization mode - low-side drivers are enabled, spi is fu lly operational. ready for initialization (see initialization requirements on page 39 ). enable mode - (normal operation). drivers are enabled; output stages follow the input command. after enable, outputs require a pulse on px_ls before corresponding hs outputs turn on, in or der to charge the bootstrap capacitor. all error pin and register bits are active if detected. fault protection mode - drivers are turned off or disabled per the fault and protection mode registers. recovery requires initialization (see initialization requirements on page 39 ). table 7. functional ratings (t j = -40 c to 150 c and supply voltage range v sup = v pwr = 5.0 v to 45 v, c = 0.47 f) characteristic value default state of input pin px_ls, en1, en2, rstb, si, sclk, if left open (59) (driver output is switched off, high-impedance mode) low (<1.0 v) default state of input pin px_hs , csb if left open (59) (driver output is switched off, high-impedance mode) high (>2.0 v) notes 59. to assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.
32 nxp semiconductors 34gd3000 figure 16. device operational flow diagram sleep mode initialization standby mode fault protection enable (normal) mode sleep rstb n y stby en y n enable ls ls toggle hs toggle y ny n driver off disable driver desat/ vls uv y y n n enable hs desat vls uv en rstb disabled n n n y y y y n y n holdoff active phase desat/ phase driver off
nxp semiconductors 33 34gd3000 7.2 logic commands and registers 7.2.1 command descriptions the ic contains internal registers to control the various operat ing parameters, modes, and interrupt characteristics. these com mands are sent and status is read via 8-bit spi commands. the ic uses th e last eight bits in a spi transfer, so devices can be daisy-chai ned. the first three bits in a spi word can be considered to be the command, with the trailin g five bits being the data. the spi logic generates a framing error and ignore the spi message if the number of received bits is not eight or not a multipl e of eight. after rstb, the first spi result returned is status register 0. 7.2.2 fault reporting and interrupt generation different fault conditions described in the previous chapters c an generate an interrupt - int pin output signal asserted high. when an interrupt occurs, the source can be read from status register 0, which is also the return word of most spi messages. faults are latched on occurrence, and the interrupt and faults are only cleared by sending the corresponding clintx command. a fault still exists continues to assert an interrupt. note: if there are multiple pending interrupts, the int line does not toggle when one of the faults clears. interrupt processin g circuitry on the host must be level sensitive to correctly detect multiple simultaneous interrupt. when an interrupt occurs, the host can query the ic by sending a null command. the return word contains flags indicating any fa ults not cleared since the clintx command was last written (rising edge of csb), and the beginning of the current spi command (falli ng edge of csb). the null command causes no changes to the state of any of the fault or mask bits. the logic clearing the fault latches occurs only when: 1. a valid command had been received(i.e. no framing error). 2. no state change occurred during the spi message (if the bit is being returned as a 0 and a fault change occurs during the mid dle of the spi message, the latch remains set). the latch is cleared on the trailing (rising) edge of the csb pulse. note: to prevent missing any faults, the clintx command should not generally clear any faul ts without being observed; i.e. it should only clear faults returned in the prior null response. table 8. command list command name description 000x xxxx null these commands are used to read ic status. these commands do not change any internal ic status. returns status register 0-3, depending on sub command. 0010 xxxx mask0 sets a portion of the interrupt mask using lower four bits of command. a ?1? bit enables interrupt generation for that flag. int remains asserted if uncleared faults are still present. returns status register 0. 0011 xxxx mask1 sets a portion of the interrupt mask using lower four bits of command. a ?1? bit enables interrupt generation for this flag. int remains asserted if uncleared faults are still present. returns status register 0. 010x xxxx mode enables desat/phase error mode. enables fullon mode. lo cks further mode changes. returns status register 0. 0110 xxxx clint0 clears a portion of the fault latch corresponding to mask0 usi ng lower four bits of command. a 1 bit clears the interrupt latch for this flag. int remains asserted if other unma sked faults are still present. returns status register 0. 0111 xxxx clint1 clears a portion of the fault latch corresponding to mask1 usi ng lower four bits of command. a 1 bit clears the interrupt latch for this flag. int remains asserted if other unma sked faults are still present. returns status register 0. 100x xxxx deadtime set deadtime with calibration technique. returns status register 0.
34 nxp semiconductors 34gd3000 7.2.3 null commands this command is sent by sending binary 000x xxxx data. this can be used to read ic status in the spi return word. message 000x xx00 reads status register 0. message 000x xx01 thr ough 000x xx11 read additional internal registers. 7.2.3.1 mask command this is the mask for interrupts. a bit set to ?1? enables the corresponding in terrupt. because of the number of mask bits, this register is in two portions: 1. mask0 2. mask1 both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. figure 17 illustrates how interrupts are enabled and faults cleared. clint0 and clint1 have the same format as mask0 and mask1 respectively, but the action is to clear the interrupt latch and stat us register 0 bit corresponding to the lower nibble of the command. 7.2.3.2 interrupt handling figure 17. interrupt handling table 9. null commands spi data bits 7 6 5 4 3 2 1 0 write000xxx00 reset null commands are described in detail in status registers on page 37 of this document. table 10. mask0 register spi data bits 7 6 5 4 3 2 1 0 write 0 0 1 0 x x x x reset 1111 table 11. mask1 register spi data bits 7 6 5 4 3 2 1 0 write0011xxxx reset 1111 to status register various faults from clint command from maskx:n register fault net 0 net n int mask bit int clear int source s r latch
nxp semiconductors 35 34gd3000 7.2.4 mode command this command is sent by sending binary 010x xxxx data. 7.2.5 deadtime command deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. the deadtime timer starts w hen a fet is commanded off (see figure 6 and figure 12 ). the deadtime control is disabled by enabling the fullon mode. the deadtime is set by sending the deadtime command (100x xxx1), and then sending a calibration pulse of csb. this pulse must b e 16 times longer than the required deadtime (see figure 18 ). deadtime is measured in cycle times of the internal time base, f tb . this measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high a nd low gate transactions in the same phase. table 12. setting interrupt masks mask:bit description mask0:0 overtemperature on any gate drive output generates an interrupt if this bit is set. mask0:1 desaturation event on any output generates an interrupt if this bit is set. mask0:2 vls undervoltage generates an interrupt if this bit is set. mask0:3 overcurrent error ?if the overcurrent comparator threshold is exceeded, an interrupt is generated. mask1:0 phase error ?if any phase comparator output is not at the expected value when an output is command on, an interrupt is generated. this signal is the xor of the phase comparator output with the output drive state, and blacked for the duration of the desatura tion blanking interval. in fullon mode, this signal is blanked and cannot generate an error. mask1:1 framing error ?if a framing error occurs, an interrupt is generated. mask1:2 write error after locking. mask1:3 reset event ?if the ic is reset or disabled, an interrupt occurs. since t he ic always starts from a reset condition, this can be used to test the interrupt mechanism because when the ic comes out of reset, an interrupt immediately occurs. table 13. mode command spi data bits 7 6 5 4 3 2 1 0 write0100 desaturation fault mode 0 fullon mode mode lock reset 0000 ? bit 0 ? mode lock is used to enable or disable mode lock. this bit can only be cleared with a device reset. since the mode lock mode can only be set, this bit prevents any subsequent, and likely e rroneous, mode, deadtime, or mask register changes from being received. if an attempt is made to write to a register wh en mode lock is enabled, a write error fault is generated. ? bit 1 ? fullon mode. if this bit is set, programmed deadtime control is disabl ed, making it is possible to have both high and low-side drivers in a phase on simultaneously. this could be useful in sp ecial applications such as alternator regulators, or switched-r eluctance motor drive applications. there is no deadtime control in full on mode. input signals directly control the output stages, synchr onized with the internal clock. this bit is a ?0?, after reset. until overwritten, the ic oper ates normally; deadtime control and logic prevents both outputs f rom being turned on simultaneously. ? bit 3 ? desaturation fault mode controls what happen when a desaturation event is detected. when set to ?0?, any desaturation on any channel causes all six output drivers to shutoff. the drivers can only be re-enabl ed by executing the clint command. when 1 , desaturation faults are completely ignored. bit 3 controls behavio r if a desaturation, or phase error event is detected. the po ssibilities are: ? 0: default: when a desaturation, or phase error event is detected on any channel, all channels turn off and generates an interrupt, if interrupts are enabled. ? 1: disable: desaturation /phase error channel shutdown is disabled, but interrupts are still possible if unmasked. sending a mode command and setting the mode lock simultaneously are allowed. this sets the requested mode and locks out any fur ther changes.
36 nxp semiconductors 34gd3000 for example: the internal time base is running at 20 mhz and a 1.5 s deadtime is required. first a deadtime command is sent (u sing the spi), then a csb is sent. the csb pulse is 16*1.5 = 24 s wide. the ic measures this pulse as 24000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in the deadtime register. until the next deadtime calibration is performed, 30 clock cycles separates the tu rn off and turn on gate signals in the same phase. the worst case error immediately after calibration is +0/-1 time base cycle, for this e xample +0 ns/ -50 ns. note that if the internal time base drifts, the effect on deadtime scales directly. sending a zero deadtime command (100x xxx0) se ts the deadtime timer to 0. however, si multaneous turn-on of high-side and low-si de fets in the same phase is still prevented unless the fullon co mmand has been transmitted. ther e is no calibration pulse expecte d after receiving the zero deadtime command. after reset, deadtime is set to the maximum value of 255 ti me base cycles (typically 15 s). the ic ignores any spi data sent during the calibration pulse. if there are any transitions on si or sclk while the deadtime cs b pulse is low, a framing error is generated, however, the csb pulse is used to calibrate the deadtime. figure 18. deadtime calibration table 14. .deadtime command spi data bits 7 6 5 4 3 2 1 0 write 1 0 0 x x x x zero/calibrate reset xxxx cs sclk si so deadtime command deadtime calibration pulse deadtime calibration pulse deadtime command cs sclk si so
nxp semiconductors 37 34gd3000 7.2.6 status registers after any spi command, the status of the ic is reported in the return value from the spi port. there are four variants of the n ull command used to read various status in the ic. other commands return a general status word in the status register 0. there are four status registers in the ic. status register 0 is most commonly used for general status. registers one through th ree are used to read or confirm internal ic settings. 7.2.6.1 status register 0 (status latch bits) this register is read by sending the null0 command (000x xx00). it is also returned after any other command. this command retur ns the following data: table 15. status register 0 spi data bits 7 6 5 4 3 2 1 0 results register 0 read reset event write error framing error phase error overcurrent low vls desat detected on any channel tlim detected on any channel reset10000000 all status bits are latched. the latches are cleared only by send ing a clint0 or clint1 command with the appropriate bits set. if the status is still present, this bit does not clear. clint0 and clin t1 have the same format as mask0 and mask1 respectively. ? bit 0 ?is a flag for overtemperature on any channel. this bit is the or of the la tched three internal tlim detectors.this flag can generate an interrupt if the appropriate mask bit is set. ? bit 1 ?is a flag for desaturation detection on any channel. this bit is the or of the latched three internal high-side desaturation detectors and phase error logic. faults are also detected on the low-side as phase errors . a phase error is generated if the output signal (at px_hs_s) does not properly reflec t the drive conditions. the phase error is the triple or of phase errors from each phase. each phase error is the or of the hs and ls phase errors. an hs phase error (which also triggers the desaturation detector) occ urs when the hs fet is commanded on, and the px_hs_s is still low in the deadtime duration after it is driven on. similarly, an ls phase error occurs when the ls fet is commanded on, and the px_hs_s is st ill high in the deadtime duration after the fet is driven on . this flag can generate an interrupt if the appropriate mask bit is set. ? bit 2 ? is a flag for low supply voltage . this flag can generate an interrupt if the appropriate mask bit is set. ? bit 3 ?is a flag for the output of the overcurrent comparator . this flag can generate an interrupt if the appropriate mask bit is set. ? bit 4 ?is a flag for a phase error . if any phase comparator output is not at the expected value when just one of the individual high or low-side outputs is enabled, the fault flag is set. this signal is the xor of the phase comparat or output with the output drive r state, and blanked for the duration of the desaturation blanking interval. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 5 ?is a flag for a framing error . a framing error is a spi message not containing one or more multiples of eight bits. sclk toggling while measuring the deadtime calibration pulse is also a framing error. this would typically be a transient or permanent hardwa re error, perhaps due to noise on the spi lines. this flag can gene rate an interrupt if the appropriate mask bit is set. ? bit 6 ?indicates a write error after the lock bit is set. a write error is any attempted write to the maskn, mode, or a deadtime command after the mode lock bit is set. a write error is any attempt to write any other command than the one defined in the table 8 . this would typically be a software error. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 7 ?is set upon exiting rstb . it can be used to test the interrupt mechanism or to flag for a condition where the ic gets reset without the host being otherwise aware. this flag can generate an interrupt if the appropriate mask bit is set.
38 nxp semiconductors 34gd3000 7.2.6.2 status register 1 (mode bits) this register is read by sending the null1 command (000x xx01). this is guaranteed to not affect ic operation and returns the f ollowing data: 7.2.6.3 status register 2 (mask bits) this register is read by sending the null2 command (000x xx10). this is guaranteed to not affect ic operation and returns the f ollowing data: 7.2.6.4 status register 3 (deadtime) this register is read by sending the null3 command (000x xx11). this is guaranteed to not affect ic operation and returns the f ollowing data: table 16. status register 1 spi data bits 7 6 5 4 3 2 1 0 results register 1 read 0 desaturation mode zero deadtime set calibration overflow deadtime calibration 0 fullon mode lock bit reset00000000 ? bit 0 ? lock bit indicates the ic registers (deadtime, maskn, clintn, and mode) are locked. any subsequent write to these registers is ignored and sets the write error flag. ? bit 1 ? is the present status of fullon mode . if this bit is set to ?0?, the fullon mode is not allowed. a ?1? indicates the ic can operate in fullon mode (both high-side and low-side fets of one phase can be turned on simultaneously). ? bit 3 ?indicates deadtime calibration occurred. it is ?0? until a successful deadtime command is executed. this includes the zero deadtime setting, as well as a calibration overflow. ? bit 4 ?is a flag for a deadtime calibration overflow . ? bit 5 ?is set if zero deadtime is commanded. ? bit 6 ?reflects the current state of the desaturation /phase error turn-off mode. table 17. status register 2 spi data bits 7 6 5 4 3 2 1 0 results register 2 read mask1:3 mask1:2 mask1:1 mask1:0 m ask0:3 mask0:2 mask0:1 mask0:0 reset11111111 table 18. status register 3 spi data bits 7 6 5 4 3 2 1 0 results register 3 read dead7 dead6 dead5 dead4 dead3 dead2 dead1 dead0 reset00000000 these bits represent the calibration applied to the internal osc illator to generate the requested deadtime. if calibration is n ot yet performed, all these bits return 0 even though the actual dead time is the maximum.
nxp semiconductors 39 34gd3000 7.3 initialization requirements the 34gd3000 provides safe, dependable gate control for three phase bldc motor control units when properly configured. however, if improperly initialized, the high-side gate drive can be left in a high-impedance mode which allows charge to accumulate from ex ternal sources, eventually turning on the high-side output transistor . it is prudent to follow a well defined initialization procedure which establishes known states on the gates of all the phase drivers before any current flows in the motor. 7.3.1 recovery from sleep mode (reset) the output gate drive is pulled low with the hold off circuit as long as v ls is low, there is a power on reset condition, or +5.0 v is low. these conditions are present during a reset condition. when first coming out of a reset condition, the gate drive circuits are in a h igh-impedance state until the first command is given for operation. after the reset line goes high, the supplies begin to operate and the hol d off circuit is deactivated. the phase input lines does not have any effect on the gate drive until both enable1 and enable2 go high and even t hen, the low-side gate must be commanded on before the high-side gate can be operated. this is to insure the bootstrap capacitor has been charged before commencing normal operation. then the high-side gate must be commanded on and then off to initialize the output latches. a proper initialization sequence places the output gate drives in a low-impedance known condition prior to releasing t he device for normal operation. a valid initialization sequence would go something like this: 1. reset goes high (enable1 and enable2 remain low) 2. spi commands to configure valid interrupts, desat mode and deadtime are issued 3. spi command to clear all interrupt conditions 4. enable1 and enable2 are set high (ls outputs are now enabled) 5. pa_ls, pb_ls, and pc_ls are toggled high for about 1.0 s (hs outputs are enabled, but not latched) 6. toggle npa_hs, npb_hs, and npc_hs low for deadtime plus at least 0.1 s (hs outputs are now latched and operational). end of initialization. doing step 6 simultaneously on all hs inputs places the motor into high-side recirculation mode and does not cause motion durin g the time they are on. this action forces the high-side gate drive out of tri-state mode and leave it with the hs_g shorted to hs_s on all phases. the hs output fets are off and ready for normal motor control. step 5 and step 6 can be done on all the stated inputs simultaneously. it may be desirable for the hs (step 6) to be toggled simultaneously to prevent current from flowing in the motor during initialization. note the inputs pa_ls, pb_ls, pc_ls, npa_hs, npb_hs, and npc_hs are edge sensitive. toggling the ls inputs enables the hs drivers, so for the hs drivers to be initialized correctly the edge of the input signal to the hs drivers must come after the l s input toggle. a failure to do this results in the hs gate output remaining in a high-impedance mode. this can result in an accumulation of ch arge, from internal and external leakage sources, on the gate of the hs output fet causing it to turn on even though the input level to th e 34gd3000 appears to indicate it should be off. when this happens, the logic of the 34gd3000 allows the ls output fet to be turned on wit hout taking any action on the hs gate because the logic is still indicating the hs gate is off. the initial ls input transition from low to high needs to be after both enable inputs are high (the device in normal mode) for the same reason. the delay between enable and the ls in put should be 280 ns minimum to insure the device is out of stby mode . once initialized the output gate drives continues to operate in a low- impedance mode as commanded by the inputs until the next reset event.
40 nxp semiconductors 34gd3000 figure 19. full initialization table 19. full initialization timing description time description min comments t pu_vdd , t pu_vls power up time from reset 2.0 ms reset must remain high long enough for v dd and v ls to reach the full regulated voltage. the normal time for this to oc cur is specified as 2.0 ms maximum. if there is more capacitance on v ls or v dd than the normal values given in the specification, this time may need to be increased. in general, the time may be safely sca led linearly with the capacitance. if the charge pump is used, it may also increase this time. an estimate of increased time, due to the charge pump, would be to add 25%. for example, the nominal v ls capacitance is 2.2 f on each pin, the power up time should be increased to 4.0 ms, 5.0 ms if using the charge pump. t 1 end of spi communication to en1 and en2 rising edge 0 ns t 2 en1 and en2 rising edge to first ls output command 280 ns restricted by en1 and en2 propagation delay t 3 initial ls on period 1.0 s nominally 1.0 s is more than enough. the calculated value is 5*c boot (r sense + r ds(on)_ls ). 100 ns for default recovery. t 4 ls off to hs on 0 ns no defined maximum, but hs is undefined until beginning of toggle on the hs t 5 initial hs on period 100 ns + dead time minimum: deadtime + 100 ns to guarantee the hs is switched. maximum: same limitations as normal operation. unlimited time if leakage currents are less than trickle charge pump margin. t 6 hs off to normal operation 0 ns immediately begin normal operation int spi csb px_hsb px_ls en1-2 rstb vdd vls vpwr vsup t pu_vdd t pu_vls t 1 t 2 t 4 t 5 t 6 t 3
nxp semiconductors 41 34gd3000 7.3.2 recovery from standby mode or a fault when the 34gd3000 is placed in standby mode or a fault condition causes a shutdown, the gate outputs are all driven low. the hi gh-side gate drive is then disabled and locked to prevent unauthorized tr ansitions. this requires an initialization sequence to recover normal operation at the end of this mode of operation. the initializati on sequence is nearly identical to recovery from sleep mode, wi th the modification the initial pulse to the low-side control inputs can be reduced to a 100 ns pulse (the low-side gates may not actu ally change state). then the initialization is completed by cycling the high-s ide gates to re-engage the gate drive and insure it is in the proper state prior to resuming normal operation. a valid initialization sequence goes something like this: 1. spi command to clear all interrupt conditions 2. enable1 and enable2 are set high (ls outputs are now enabled) 3. pa_ls, pb_ls and pc_ls are toggled high for at least 100 ns (h s gate drive outputs are enabled) longer if bootstrap capacitor s need charged. 4. toggle npa_hs, npb_hs, and npc_hs low for deadtime plus at least 100 ns. end of initialization. doing step 4 simultaneously on all hs inputs places the motor into high-side recirculation mode and does not cause motion durin g the time they are on. this action restores the high-side gate drive operation and leaves it with the hs_g shorted to hs_s on all phases. the hs outpu t fets are off and ready for normal motor control. step 3 and step 4 can be done on all the stated inputs simultaneously. in fact, it is desirable for the hs (step 4) to be toggl ed simultaneously to prevent current from flowing in the motor during initialization. note the inputs pa_ls, pb_ls, pc_ls, npa_hs, npb_hs, and npc_hs are edge sensitive. toggling the ls inputs enables the hs drivers, so for the hs drivers to be initialized correctly the edge of the input signal to the hs drivers must come after the l s input toggle. a failure to do this results in the hs gate output remaining locked out from input control. the initial ls input transition fro m low to high needs to be after both enable inputs are high (the device in normal mode) for the same reason. the delay between enable and the ls input should be 280 ns minimum to insure the device is out of stby mode. figure 20. recovery initialization the horizontal divisions are not to scale, they are a reference to show the sequence of operation. either individual npx_hs and px_ls or npx_combined may be used. npx_combined is defined as both npx_ hs and px_ls tied together or operated to the same logic level simultaneously. int spi ncs px_combined npx_hs px_ls en2 en1 clear 0.1 s 0.1 s
42 nxp semiconductors 34gd3000 7.3.3 ic initialization this process flow initializes the ic and its software environment. 1. apply power (v sys ) to module 2. remove rstb (rstb goes high, en1 and en2 are still low) 2.1. when rstb rises above the threshold, the device powers up. the charge pump (if configured) starts and allows v dd and v ls to stabilize. 3. initialize registers 3.1. clear all interrupt status flags (send cint0 and cint1) 3.2. initialize mask register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. 3.3. set desired deadtime either by commanding zero dead time or calibrating the dead time. 3.4. send mode command with desired bits, and also the lock bit. e.g. 01000001. this prevents further mode changes. 4. bring en1 & en2 high 5. initialize the outputs 5.1. command all px_hsb to logic 1 (high-side off) 5.2. command all px_ls to logic 1 (commanding low-side on). the input must transition from low to high after en1 and en2 have gone high. 5.3. wait for the bootstrap capacitors to charge (about 1.0 s typically) 5.4. command all px_ls to logic 0 (command low-side off) 5.5. command all px_hsb to logic 0 (command high-side on) 5.6. command all px_hsb to logic 1 (command high-side off) the device is now ready for normal operation. 7.3.4 interrupt handler when an interrupt occurs, the general procedure is to send null0 and null1 commands to determine what happened, take corrective action (if needed), clear the fault, and return. because the return value from an spi command is actually returned in the subsequent message, main-loop software trying to read sr1, sr2, or sr3, may experience an interrupt between sending the spi command and the subsequent read. if these registers are to be read, special care must be taken in the software to ensure the correct results are being interpreted.
nxp semiconductors 43 34gd3000 8 typical applications figure 21. typical application diagram using charge pump vsup vpwr pump vpump pgnd main charge pump oscillator uv detect 5v reg. vdd control logic t-lim rst en1 en2 int px_hs px_ls 3 3 cs si sclk so phase_x 3 oc_out oc_th amp_out amp_n amp_p vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot vdd vls trickle charge pump hold -off circuit high -side driver low -side driver vls reg. i-sense amp. over-cur. comp. phase comp. desat. comp. to motor 3 x + - + - v sys + - vsup vsup 1.4v gnd to other two phases +12v nom. phase x output to adc r g_hs r g_ls (optional) (optional) c x_boot r sense phase return vpwr pump d1 d2 c1 c2 c6 c3 c5 c4 r1 r2 r3 r fb q hs q ls
44 nxp semiconductors 34gd3000 figure 22. power dissipation profile of application using charge pump reference application with: ? pump capacitor: 1.0 f mlc ? pump filter capacitor: 47 f low esr aluminum electrolytic ? pump diodes: mur120 ? output fet gate charge: 240 nc at 10 v ? pwm frequency: 20 khz ? switching single phase below approximately 17 v the charge pump is actively regulating v pwr . the increased power dissipation is due to the charge pump losses. above this voltage the charge pump oscillator shuts down and v sys is passed through the pump diodes directly to v pwr . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 5 10152025303540 supply voltage (v) power dissipated (w)
nxp semiconductors 45 34gd3000 figure 23. power dissipation profile of application not using charge pump reference application with: ? output fet gate charge: 240 nc at 10 v ? pwm frequency: 20 khz ? switching single phase ? no connections to pump or vpump ? vpwr connected to v sys if v pwr is supplied by a separate pre-regulator, the power dissipation pr ofile is nearly flat at the value of the pre-regulator voltag e for all v sys voltages. 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 1.500 10 15 20 25 30 35 40 45 50 55 60 supply voltage (v) power dissipation (w)
46 nxp semiconductors 34gd3000 9 packaging 9.1 package mechanical dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing?s document number. . table 20. packaging information package suffix package outline drawing number 56-pin qfn ep 98asa00654d
nxp semiconductors 47 34gd3000
48 nxp semiconductors 34gd3000
nxp semiconductors 49 34gd3000 10 revision history revision date description of changes 1.0 4/2015 ? initial release 2.0 6/2015 ? updated thermal resistance value and unit in table 3 7/2015 ? changed part number from pc to mc in the orderable parts on page 2 11/2015 ? restated the feature - gate drive capability of 1.0 a to 2.5 a, on page 1 3.0 12/2015 ? corrected upper end operating range value on page 1 ?corrected v sup value in table 3 5/2016 ? corrected application description ? updated to nxp form and style
information in this document is provided solely to enabl e system and software implementers to use nxp products. there are no expressed or implied copy right licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regard ing the suitability of its products for any particular purpose, nor does nxp assume any liabi lity arising out of the application or use of any product or circuit, and specifically disclaims any and all liabilit y, including without limitation, consequent ial or incidental damages. "typical" parameters that may be provided in nxp data sheets and/or specifications can and do va ry in different applications, and actual performance may vary over time. all operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html . how to reach us: home page: nxp.com web support: http://www.nxp.com/support nxp, the nxp logo, freescale, the freescale logo, and sm artmos are trademarks of nxp b.v. all other product or service names are the property of thei r respective owners. all rights reserved. ? 2016 nxp b.v. document number: mc34gd3000 rev. 3.0 5/2016

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